The most well-known cryptographic functions include, for example:                the Rivest Shamir Adleman (RSA) algorithm, based on a modular exponentiation operation,        the Elliptic Curve Cryptography (ECC) family of algorithms, based on the principle of the elliptic curve discrete logarithm, which implements a scalar multiplication operation, this operation using the main modular arithmetic operations of addition, subtraction, multiplication, and inversion,        the Diffie-Helmann algorithm, based on the principle of the discrete logarithm on integers, implementing the modular exponentiation operation,        the Rabin-Miller probabilistic primality algorithm, based on the modular exponentiation operation.        
They are implemented by security protocols, such as the Secure Sockets Layer (SSL) or Internet Key Exchange (IKE) protocol.
The three major characteristics that a cryptographic integrated circuit should optimize are:                its ability to support a large number of protocols and thus cryptographic algorithms, which forces it to implement the main standard functions of the modular arithmetic, including addition, subtraction, multiplication, division, reduction, inversion, exponentiation, and scalar multiplication,        its performance in terms of the number of protocol operations it can carry out per second, such as the number of SSL transactions per second or even the number of IKE key exchanges per second, these performances being directly related to the number of underlying arithmetical operations it can execute per second,        its resistance to various attacks designed to retrieve secret data used during the execution of a cryptographic algorithm, such as simple power analysis (SPA) or differential power analysis (DPA) attacks, which measure the currents and voltages going in and out of the integrated circuit.        
Regarding this third characteristic to be optimized, the circuit preferably integrates a specific implementation of cryptographic algorithms, generally described as counter-measure implementation, which is implemented at the expense of performance.
A first solution for at least partly optimizing these characteristics involves designing integrated circuits with specialized hardware, called application-specific integrated circuits (ASICs). These circuits are custom designed. They have the advantage of a reduced product cost, full control of implemented functions, and high performance because the functions they support are wired into the circuit. However, this results in a long and costly development that can be recovered only in a market that is capable of absorbing large quantities of integrated circuit products, such as the U.S. market.
By contrast, in Europe, because there is less volume produced and fewer means of investment, a second solution is adopted, based on a technology of programmable integrated circuits, such as field-programmable gate array (FPGA) technology, which implements a programmable main processor with an internal memory. This second solution associates the programmable main processor of the FPGA circuit to specific integrated circuits and redirects some cryptographic functions that are normally performed by the main processor, such as modular multiplication, exponentiation, or even scalar multiplication, to these integrated circuits that are physically dedicated to such functions. These dedicated circuits are called hardware accelerators. Although this solution can increase the performance of the FPGA circuit, the hardware accelerators must be replaced when it is needed to perform a counter-measure. Also, place and route of the integrated circuit becomes necessary whenever there is a change to the microcode executed by the main processor. “Place and route” means the process during which the various parts of an integrated circuit are automatically positioned and connected.
Using FPGA technology, it would also be impossible to have a pure software solution that involves programming the main processor because the processors in FPGA circuits are usually 32-bit processors that operate at frequencies below 200 MHz, making such a solution especially slow. Moreover, although possible in theory, running multiple processors in parallel in a single FPGA circuit would quickly become limited due to insufficient internal memory. It would then be necessary to use external random access memory (RAM).
It may therefore be desirable to provide a cryptographic integrated circuit that can overcome at least some of the above mentioned problems and constraints.